1. Field of the Invention
The present invention generally relates to a phase locked loop (PLL) device, and more particular, to an H-sync phase locked loop device for a TV video signal.
2. Description of Related Art
A TV video signal includes a video frame signal and timing information so as to correctly retrieve the original video signal in a receiving TV set or display. The timing information mainly is a synchronization signal mixed in the video signal, so that after a receiving terminal obtains the video signal and the synchronization signal is correctly decoded, the corresponding video frames are generated. The synchronization signal is usually termed as ‘sync’. Hence, how to correctly obtain the sync from a video signal is very fundamental to process a video signal, and a phase-locked loop circuit (PLL) is usually adopted to quickly, continuously and stably obtain the phase of the sync.
The basic overall function of a PLL is to use an oscillation source with an extremely-low frequency variation as the oscillation reference, adopt a closed-loop control system for feedback and drive a frequency-variable component, so that a target signal is synchronized with the oscillation source, i.e. the target signal is phase locked.
Referring to FIG. 1, it is an architecture diagram of a conventional H-sync phase locked loop circuit for a TV video signal. The H-sync phase-locked loop circuit (H-sync PLL) 100 of FIG. 1 is in charge of correctly and effectively obtaining an H-sync. The H-sync PLL includes a phase-locked loop latch (PLL latch) 102, an analog-to-digital converter (ADC) 110 (marked by A/D in FIG. 1), an auto-gain-control and clamping circuit (AGC and clamping circuit) 120, a slice level calculator 130, a phase-error detector 140, a digital gain and low-pass filter 150, a discrete time oscillator 160, an increment step number calculator 170 and a H-sync detection counter 180.
The PLL latch 102 is used for outputting a system timing signal 104 having a frequency FS to support the operation of the whole system including providing the ADC 110 with a sampling frequency. When the ADC 110 receives a TV video signal 105 containing an H-sync, the signal 105 is converted into a digital TV video signal 112. After that, the digital TV video signal 112 is sent to the AGC and clamping circuit 120 to perform an AGC and clamping processing to produce a clamped signal 122 with a controlled amplitude, and then the signal 122 is output to the slice level calculator 130 and the phase-error detector 140.
Once the slice level calculator 130 receives the clamped signal 122, a middle level of the H-sync is estimated and the estimated middle level 132 is output to the phase-error detector 140. On the other hand, the phase-error detector 140 receives the clamped signal 122, the estimated middle level 132 of the H-sync from the slice level calculator 130 and an H-sync phase signal (H-phase signal) 12 from the H-sync detection counter 180. The phase-error detector 140 generates a signal falling and rising transient according to the comparison result between the clamped signal 122 and the middle level 132 estimated by the slice level calculator 130, calculates the dynamic error of the H-phase signal 182 therewith and further generates a phase-error signal 142 output to the digital gain and low-pass filter 150.
The H-phase signal 182 is output from the H-sync detection counter 180, while the H-sync detection counter 180 receives a timing signal 162 with a frequency Fdto output from the discrete time oscillator 160 and a preset required total pixel quantity output from each line (H-sync total) HT. In fact, the H-sync total HT is the reciprocal of the frequency for each line to output pixels FO, which would be explained hereinafter. Every period course of the timing signal 162 with the frequency Fdto, the number indicated by the counter 180, i.e. the H-phase signal output therefrom, would be increased by one until the H-phase signal reaches ½HT where the H-phase signal is reset as −½HT.
After the phase-error signal 142 is processed by the digital gain and low-pass filter 150, a dynamic increment step number 152 is output to the discrete time oscillator 160. The increment step number calculator 170 receives a signal with a predetermined H-sync frequency FH and a predetermined frequency for each line to output pixels FO and outputs a regular increment step number 174 to the discrete time oscillator 160, and then the discrete time oscillator 160 adjusts the frequency Fdto of the timing signal 162 according to the regular increment step number 174 and the dynamic increment step number 152.
The H-sync frequency FH and the frequency for each line to output pixels FO are predetermined according to the format of the received TV video signal 105. For example, the NTSC format TV signal follows the communication standard of the National Television Standards Committee (NTSC), while the PAL formal TV signal and SECAM format TV signal respectively follow the standard of the Phase Alternating Line and the standard of the Sequential Color and Memory. Hence, the frequencies of the above-mentioned TV signals and the H-syncs thereof are certain.
However in fact, the H-sync of a TV video signal significantly deviates from the format standard caused by the transmission or other problems; thus, if a receiver still adopts the predetermined H-sync frequency FH, the PLL thereof would fail to effectively lock the H-sync phase of the TV video signal and a very poor TV image effect would be resulted.
In addition, if a TV system enterprise provides a TV video signal other than the above-mentioned, for example, other than the NTSC signal, the PAL signal or the SECAM signal, the H-sync deviation problem of the TV video signal would get more serious where it is unable to predetermine an appropriate H-sync frequency FH at all.